Flash memory is a type of long life span, non-volatile memory. The flash memory may maintain stored data information, even when the power is off. As such, the flash memory is often used to store configuration information. For example, data may be stored in the basic input output system (BIOS) of personal computers, personal digital assistant (PDA), and digital cameras, etc.
FIG. 1 shows a circuit diagram of an existing memory array 100. As shown in FIG. 1, taking a 4-row and 192-column memory array as an example, the memory array 100 includes a plurality of memory columns. The memory cells in the memory columns are flash memory cells. The drains of the memory cells in each columns of the memory array 100 are coupled to the bit lines corresponding to the memory columns, such as the bit lines b1<0>, b1<1> . . . b1<190>, and b1<191> illustrated in FIG. 1. The control gates of the mth rows of flash memory cells in the plurality of memory columns are coupled to the control gates of the (m+1)th rows of flash memory cells in the plurality of memory columns; and coupled to the corresponding control gate lines, such as control gate lines cg<0> and cg<1> illustrated in FIG. 1. The sources of the mth rows of flash memory cells in the plurality of memory columns and the sources of the (m+1)th rows of flash memory cells in the plurality of memory columns are configured to receive the source line signals, such as source line signals s1<0> and s1<1> illustrated in FIG. 1. Further, the select gates of the flash memory cells in a same row of memory cells in the plurality of memory columns are respectively coupled to a same work line, such as work lines w1<0>, w1<1>, w1<2> and w1<3>, where m≥1; and m is an odd number.
During the reading operation of the memory array 100, the source of a to-be-read flash memory cell 10 in the memory array 100 needs to be pulled down to a potential of 0 V. The existing technologies often utilize relatively large pull down devices, such as NMOS transistors including the pull down devices 20, 30, 40, and 50, to couple the source of the to-be-read flash memory cell 10. Further, the pull down signal slpd<0> turns on the pull down devices 20 and 30 to pull down the source of the to-be-read flash memory cell 10 to ground, i.e., a potential of 0 V relative to the ground. If the to-be-read flash memory cell is in the third row or the fourth row of the memory array 100, the pull down devices 40 and 50 are turned on by the pull down signal slpd<1> to pull down the source of the to-be-read flash memory 10.
However, the paths between the source of the to-be-read flash memory cell 10 in the memory cell array 100 and the pull down devices have certain impedances. Specifically, the paths have metal resistors and diffusion resistors. Thus, in reality, the potential of the source of the to-be-read flash memory is not 0 V. Such a condition significantly affects the reading performance of the to-be-read flash memory cell 10. Especially when the number of the columns in the memory array 100 is relatively large, the impedance issue is more severe; and the reading performance of the flash memory cell is worse.
FIG. 2 illustrates a schematic of the equivalent resistors between the to-be-read flash memory cell 10 and the pull down devices in the existing memory array 100. As shown in FIG. 2, the source of the to-be read flash memory cell 10 outputs a source current Is1. The paths for the source current Is1 flowing into the pull down device 20 and the pull down device 30 can be equivalent to metal resistors RM_L, RM_M and RM_R, and diffusion resistors Rdiff_L and Rdiff_R. The existing technologies often connect the metal resistors and the diffusion resistors with the other resistors in parallel to reduce the resistances of the metal resistors and the diffusion resistors in the circuit. Specifically, as shown in FIG. 2, the resistors R1, R2, R3 and R4 are connected in the circuit. Connecting the resistors in parallel is able to reduce the resistances of the metal resistors and the diffusion resistors in the circuit to a certain extent; and cause the potential of the sources of the flash memory cell 10 to be closer to 0 V to improve the reading performance of the flash memory cell 10. However, the improvement of the reading performance of the flash memory cell 10 has a certain limitation. Further, extra mask areas are needed in the circuit design; and the power consumption of the memory array 100 is increased.
Therefore, the existing memory arrays still have the reading performance issues. The disclosed memory array structures, and memory reading, programming and erasing methods are directed to solve one or more problems set forth above and other problems in the art.